DTS DTB Files bearbeiten



  • ACHTUNG, nur was für erfahrene Nutzer. Beschädigungen der Hardware nicht ausgeschlossen!! Also, Hirn einschalten!!

    Diese kleinen Platinen haben ja unzählige Funktionen, Ein- und Ausgänge usw. Das ganze muss ja irgendwie konfiguriert werden. Auf den ARM-Boards macht man das mit DTB Files.

    Wir nehmen mal eine geflashte SD-Karte und stecken die in einen Kartenleser. Dann öffnen wir die Boot Partition.

     frank@frank-MS-7A34 /media/frank/boot $ ls -la
     insgesamt 25272
     drwxr-xr-x  3 frank frank    16384 Jan  1  1970 .
     drwxr-x---+ 3 root  root      4096 Jun 13 13:35 ..
     -rw-r--r--  1 frank frank    69042 Jun 13 13:00 dtb
     drwxr-xr-x  2 frank frank     2048 Jun 10 20:44 extlinux
     -rw-r--r--  1 frank frank 19425288 Jun 10 20:45 Image
     -rw-r--r--  1 frank frank  6358282 Jun 10 20:45 initrd.img
    

    Das File was uns interessiert ist das File mit dem Namen dtb Dieses File kann man aber nicht so ohne weiteres bearbeiten, wie aber so oft unter Linux, gibt es für fast alles ein Tool. In diesem Fall heißt das Tool dtc (devive tree compiler) Das kann man so installieren.

    sudo apt-get install device-tree-compiler
    

    Dieser Compiler kann aus dem File dtb, was ein Binärfile ist, ein lesbares Textfile generieren und anders rum.

    Aus dem dtb File ein lesbares File erzeugen!

    cp /media/frank/boot/dtb /home/frank/dts
    dtc -I dtb -O dts -o testfile dtb
    
    • /media/frank/boot ist der Mountpoint
    • /home/frank/dts ist mein Testordner zum Spielen

    In dem Beispiel kopiere ich das File dtb von der SD-Karte in mein Testverzeichnis. Im nächsten Schritt wird dann aus dem dtb File das lesbare Textfile mit Namen testfile erzeugt.

    Dieses könnt ihr dann mit Eurem Lieblings Texteditor öffnen.

    code testfile
    

    Dann ist die Datei lesbar und änderbar.

    Beispiel (gekürzt)

    /dts-v1/;
    
    / {
    	compatible = "pine64,rockpro64", "rockchip,rk3399";
    	interrupt-parent = <0x1>;
    	#address-cells = <0x2>;
    	#size-cells = <0x2>;
    	model = "Pine64 RockPro64";
    
    	ddr_timing {
    		compatible = "rockchip,ddr-timing";
    		ddr3_speed_bin = <0x15>;
    		pd_idle = <0x0>;
    		sr_idle = <0x0>;
    		sr_mc_gate_idle = <0x0>;
    		srpd_lite_idle = <0x0>;
    		standby_idle = <0x0>;
    		auto_lp_dis_freq = <0x29a>;
    		ddr3_dll_dis_freq = <0x12c>;
    		phy_dll_dis_freq = <0x104>;
    		ddr3_odt_dis_freq = <0x29a>;
    		ddr3_drv = <0x28>;
    		ddr3_odt = <0x78>;
    		phy_ddr3_ca_drv = <0x28>;
    		phy_ddr3_dq_drv = <0x28>;
    		phy_ddr3_odt = <0xf0>;
    		lpddr3_odt_dis_freq = <0x29a>;
    		lpddr3_drv = <0x22>;
    		lpddr3_odt = <0xf0>;
    		phy_lpddr3_ca_drv = <0x22>;
    		phy_lpddr3_dq_drv = <0x22>;
    		phy_lpddr3_odt = <0xf0>;
    		lpddr4_odt_dis_freq = <0x320>;
    		lpddr4_drv = <0xf0>;
    		lpddr4_dq_odt = <0x28>;
    		lpddr4_ca_odt = <0x0>;
    		phy_lpddr4_ca_drv = <0x28>;
    		phy_lpddr4_ck_cs_drv = <0x28>;
    		phy_lpddr4_dq_drv = <0x3c>;
    		phy_lpddr4_odt = <0x28>;
    		phandle = <0x8f>;
    	};
    
    	aliases {
    		i2c0 = "/i2c@ff3c0000";
    		i2c1 = "/i2c@ff110000";
    		i2c2 = "/i2c@ff120000";
    		i2c3 = "/i2c@ff130000";
    		i2c4 = "/i2c@ff3d0000";
    		i2c5 = "/i2c@ff140000";
    		i2c6 = "/i2c@ff150000";
    		i2c7 = "/i2c@ff160000";
    		i2c8 = "/i2c@ff3e0000";
    		serial0 = "/serial@ff180000";
    		serial1 = "/serial@ff190000";
    		serial2 = "/serial@ff1a0000";
    		serial3 = "/serial@ff1b0000";
    		serial4 = "/serial@ff370000";
    		dsi0 = "/dsi@ff960000";
    		dsi1 = "/dsi@ff968000";
    		ethernet0 = "/ethernet@fe300000";
    	};
    
    	cpus {
    		#address-cells = <0x2>;
    		#size-cells = <0x0>;
    
    		cpu-map {
    
    			cluster0 {
    
    				core0 {
    					cpu = <0x2>;
    				};
    
    				core1 {
    					cpu = <0x3>;
    				};
    
    				core2 {
    					cpu = <0x4>;
    				};
    
    				core3 {
    					cpu = <0x5>;
    				};
    			};
    
    			cluster1 {
    
    				core0 {
    					cpu = <0x6>;
    				};
    
    				core1 {
    					cpu = <0x7>;
    				};
    			};
    		};
    
    		cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a53", "arm,armv8";
    			reg = <0x0 0x0>;
    			enable-method = "psci";
    			#cooling-cells = <0x2>;
    			dynamic-power-coefficient = <0x64>;
    			clocks = <0x8 0x8>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xb>;
    			sched-energy-costs = <0xc 0xd>;
    			cpu-supply = <0xe>;
    			phandle = <0x2>;
    		};
    
    		cpu@1 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a53", "arm,armv8";
    			reg = <0x0 0x1>;
    			enable-method = "psci";
    			clocks = <0x8 0x8>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xb>;
    			sched-energy-costs = <0xc 0xd>;
    			cpu-supply = <0xe>;
    			phandle = <0x3>;
    		};
    
    		cpu@2 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a53", "arm,armv8";
    			reg = <0x0 0x2>;
    			enable-method = "psci";
    			clocks = <0x8 0x8>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xb>;
    			sched-energy-costs = <0xc 0xd>;
    			cpu-supply = <0xe>;
    			phandle = <0x4>;
    		};
    
    		cpu@3 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a53", "arm,armv8";
    			reg = <0x0 0x3>;
    			enable-method = "psci";
    			clocks = <0x8 0x8>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xb>;
    			sched-energy-costs = <0xc 0xd>;
    			cpu-supply = <0xe>;
    			phandle = <0x5>;
    		};
    
    		cpu@100 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a72", "arm,armv8";
    			reg = <0x0 0x100>;
    			enable-method = "psci";
    			#cooling-cells = <0x2>;
    			dynamic-power-coefficient = <0x1b4>;
    			clocks = <0x8 0x9>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xf>;
    			sched-energy-costs = <0x10 0x11>;
    			cpu-supply = <0x12>;
    			phandle = <0x6>;
    		};
    
    		cpu@101 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a72", "arm,armv8";
    			reg = <0x0 0x101>;
    			enable-method = "psci";
    			clocks = <0x8 0x9>;
    			cpu-idle-states = <0x9 0xa>;
    			operating-points-v2 = <0xf>;
    			sched-energy-costs = <0x10 0x11>;
    			cpu-supply = <0x12>;
    			phandle = <0x7>;
    		};
    
    		idle-states {
    			entry-method = "psci";
    
    			cpu-sleep {
    				compatible = "arm,idle-state";
    				local-timer-stop;
    				arm,psci-suspend-param = <0x10000>;
    				entry-latency-us = <0x78>;
    				exit-latency-us = <0xfa>;
    				min-residency-us = <0x384>;
    				phandle = <0x9>;
    			};
    
    			cluster-sleep {
    				compatible = "arm,idle-state";
    				local-timer-stop;
    				arm,psci-suspend-param = <0x1010000>;
    				entry-latency-us = <0x190>;
    				exit-latency-us = <0x1f4>;
    				min-residency-us = <0x7d0>;
    				phandle = <0xa>;
    			};
    		};
    	};
    
    	pmu_a53 {
    		compatible = "arm,cortex-a53-pmu";
    		interrupts = <0x1 0x7 0x8 0x13>;
    	};
    
    	pmu_a72 {
    		compatible = "arm,cortex-a72-pmu";
    		interrupts = <0x1 0x7 0x8 0x14>;
    	};
    
    	psci {
    		compatible = "arm,psci-1.0";
    		method = "smc";
    	};
    
    	timer {
    		compatible = "arm,armv8-timer";
    		interrupts = <0x1 0xd 0x8 0x0 0x1 0xe 0x8 0x0 0x1 0xb 0x8 0x0 0x1 0xa 0x8 0x0>;
    	};
    
    	xin24m {
    		compatible = "fixed-clock";
    		clock-frequency = <0x16e3600>;
    		clock-output-names = "xin24m";
    		#clock-cells = <0x0>;
    	};
    
    	dummy_cpll {
    		compatible = "fixed-clock";
    		clock-frequency = <0x0>;
    		clock-output-names = "dummy_cpll";
    		#clock-cells = <0x0>;
    	};
    
    	dummy_vpll {
    		compatible = "fixed-clock";
    		clock-frequency = <0x0>;
    		clock-output-names = "dummy_vpll";
    		#clock-cells = <0x0>;
    	};
    
    	amba {
    		compatible = "arm,amba-bus";
    		#address-cells = <0x2>;
    		#size-cells = <0x2>;
    		ranges;
    
    		dma-controller@ff6d0000 {
    			compatible = "arm,pl330", "arm,primecell";
    			reg = <0x0 0xff6d0000 0x0 0x4000>;
    			interrupts = <0x0 0x5 0x4 0x0 0x0 0x6 0x4 0x0>;
    			#dma-cells = <0x1>;
    			clocks = <0x8 0xd3>;
    			clock-names = "apb_pclk";
    			peripherals-req-type-burst;
    			phandle = <0x98>;
    		};
    
    		dma-controller@ff6e0000 {
    			compatible = "arm,pl330", "arm,primecell";
    			reg = <0x0 0xff6e0000 0x0 0x4000>;
    			interrupts = <0x0 0x7 0x4 0x0 0x0 0x8 0x4 0x0>;
    			#dma-cells = <0x1>;
    			clocks = <0x8 0xd4>;
    			clock-names = "apb_pclk";
    			peripherals-req-type-burst;
    		};
    	};
    
    	ethernet@fe300000 {
    		compatible = "rockchip,rk3399-gmac";
    		reg = <0x0 0xfe300000 0x0 0x10000>;
    		rockchip,grf = <0x15>;
    		interrupts = <0x0 0xc 0x4 0x0>;
    		interrupt-names = "macirq";
    		clocks = <0x8 0x69 0x8 0x67 0x8 0x68 0x8 0x66 0x8 0x6a 0x8 0xd5 0x8 0x166>;
    		clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac";
    		resets = <0x8 0x89>;
    		reset-names = "stmmaceth";
    		power-domains = <0x16 0x16>;
    		status = "okay";
    		phy-supply = <0x17>;
    		phy-mode = "rgmii";
    		clock_in_out = "input";
    		snps,reset-gpio = <0x18 0xf 0x1>;
    		snps,reset-active-low;
    		snps,reset-delays-us = <0x0 0x2710 0xc350>;
    		assigned-clocks = <0x8 0xa6>;
    		assigned-clock-parents = <0x19>;
    		pinctrl-names = "default", "sleep";
    		pinctrl-0 = <0x1a>;
    		pinctrl-1 = <0x1b>;
    		tx_delay = <0x28>;
    		rx_delay = <0x20>;
    	};
    
    	dwmmc@fe310000 {
    		compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
    		reg = <0x0 0xfe310000 0x0 0x4000>;
    		interrupts = <0x0 0x40 0x4 0x0>;
    		clock-freq-min-max = <0x30d40 0x2faf080>;
    		clocks = <0x8 0x1ee 0x8 0x4d 0x8 0x9c 0x8 0x9d>;
    		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
    		fifo-depth = <0x100>;
    		power-domains = <0x16 0x1c>;
    		status = "okay";
    		clock-frequency = <0x2faf080>;
    		supports-sdio;
    		bus-width = <0x4>;
    		disable-wp;
    		cap-sd-highspeed;
    		cap-sdio-irq;
    		keep-power-in-suspend;
    		mmc-pwrseq = <0x1c>;
    		non-removable;
    		num-slots = <0x1>;
    		pinctrl-names = "default";
    		pinctrl-0 = <0x1d 0x1e 0x1f>;
    		sd-uhs-sdr104;
    	};
    
    	dwmmc@fe320000 {
    		compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
    		reg = <0x0 0xfe320000 0x0 0x4000>;
    		interrupts = <0x0 0x41 0x4 0x0>;
    		clock-freq-min-max = <0x61a80 0x8f0d180>;
    		clocks = <0x8 0x1ce 0x8 0x4c 0x8 0x9a 0x8 0x9b>;
    		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
    		fifo-depth = <0x100>;
    		power-domains = <0x16 0x1b>;
    		status = "okay";
    		clock-frequency = <0x2faf080>;
    		supports-sd;
    		bus-width = <0x4>;
    		cap-mmc-highspeed;
    		cap-sd-highspeed;
    		disable-wp;
    		num-slots = <0x1>;
    		vqmmc-supply = <0x20>;
    		pinctrl-names = "default";
    		pinctrl-0 = <0x21 0x22 0x23 0x24>;
    		card-detect-delay = <0x320>;
    	};
    
    	sdhci@fe330000 {
    		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
    		reg = <0x0 0xfe330000 0x0 0x10000>;
    		interrupts = <0x0 0xb 0x4 0x0>;
    		arasan,soc-ctl-syscon = <0x15>;
    		assigned-clocks = <0x8 0x4e>;
    		assigned-clock-rates = <0xbebc200>;
    		clocks = <0x8 0x4e 0x8 0xf0>;
    		clock-names = "clk_xin", "clk_ahb";
    		clock-output-names = "emmc_cardclock";
    		#clock-cells = <0x0>;
    		phys = <0x25>;
    		phy-names = "phy_arasan";
    		power-domains = <0x16 0x17>;
    		status = "okay";
    		bus-width = <0x8>;
    		mmc-hs200-1_8v;
    		supports-emmc;
    		non-removable;
    		keep-power-in-suspend;
    		phandle = <0x96>;
    	};
    

    Das dts des ROCKPro64. Nun kann man die Änderungen vornehmen und abspeichern. Danach muss man das File wieder in das Binärformat umwandeln.

    Aus dem testfile wieder ein dtb File erzeugen!

    dtc -I dts -O dtb -o dtb testfile
    cp /home/frank/dts/dtb /media/frank/boot
    

    Sollte selbsterklärend sein, macht aus dem testfile wieder ein dtb und kopiert es auf die SD-Karte zurück.

    Danach kann man dann seine Änderungen ausprobieren.



  • Hat sich was geändert?

    Neuer Pfad:

    cd /boot/dtbs/4.4.132-1066-rockchip-ayufan-g48b9d1455011/rockchip
    

    Übersetzen

    dtc -I dtb -O dts -f rk3399-rockpro64.dtb -o testfile.dts
    

    Bearbeiten

    code testfile.dts
    

    Zurück

     dtc -I dts -O dtb -f testfile.dts -o rk3399-rockpro64.dtb


  • Oder, ganz einfach

    sudo dtedit
    

    🙂


 

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